The present invention relates to a semiconductor memory device and, in particular, a word line driver circuit and word line driving method for a DRAM, that is, a generally called WL boostless DRAM, not boosting word lines.
FIG. 1 is a circuit diagram showing a memory cell of a typical DRAM. As well known in the art, in the DRAM, one memory cell MC comprises one transfer gate T (NMOS transistor) for data transfer and one capacitor C for data holding. The capacitor C is connected through the transfer gate T to a bit line BL and grounded to Vss. A word line WL is connected to the gate of the transfer gate T.
Let it be assumed that "1" data is written to the memory cell MC, that is, from the bit line BL through the transfer gate T in the memory cell MC. With a selected word line WL pulled up, a corresponding transfer gate T is turned ON. As a result, the capacitor C is charged from the bit line BL through the turned-ON transfer gate T. At this time, a potential written in the capacitor C is lowered by a threshold voltage of the transfer gate T (NMOS transistor) to prevent a fall in a write margin. It is, therefore, usual to drive the transfer gate T at about 1.5 times larger than the power supply potential (Vss). Since a voltage higher than the power supply potential Vcc is applied to the gate oxide film of the transfer gate T, the gate oxide film is thickened so as to secure reliability.
In recent years, a logic-combined DRAM has begun to be used where a logic circuit, together with a DRAM, is mounted on one chip. The logic-combined DRAM has the following problem. In order to implement the manufacturing process efficiently, the logic circuit section and DRAM section are manufactured in the same step. The gate oxide film of a transistor in the logic circuit section is so formed as to have the same thickness as the gate oxide film of the transfer gate T of the DRAM. For this reason, the transistor of the logic circuit section involves a fall in a current drive capability and the operation speed is slowed down. If the logic circuit section is formed in a different manufacturing process from that of the DRAM section, such a problem is not involved, but the manufacturing cost greatly increases due to an increase in the number of steps involved.
In order to solve such problem, a DRAM (hereinafter referred to as a WL boostless type DRAM) has been proposed. FIG. 2 is a circuit diagram diagrammatically showing a power supply system of a WL boostless type DRAM. This circuit comprises a memory cell amplifier 11, sense array 12, word line driver circuit 13, DRAM peripheral circuit 14, I/O buffer 15, negative potential Vbb generation circuit (Vbb generator circuit) 16, DC regulator 17, etc. The memory cell array 11 and sense amplifier 12 are operated by the output potentials of the DC regulator 17 and Vbb generator 16. The word line driver circuit 13 is operated by the output potential Vbb of the power supply potential Vcc and. The DRAM peripheral circuit 14, I/O buffer 15 and Vbb generator circuit 16 are operated across the supply potentials Vcc and Vss.
FIG. 3 is a circuit diagram showing a word line driver circuit 13 in FIG. 2. It is to be noted, however, that FIG. 3 shows a circuit corresponding to one word line. The word line driver circuit 13 comprises a three-input NAND type gate 18, PMOS transistors 19, 20 and 21 and NMOS transistors 22 and 23. Address signals XAj, XBk and XCl are supplied respectively to the input terminals of the NAND gate 18. The output terminal of the NAND gate 18 is connected to the source of the transistor 19, drain of the transistor 20 and gate of the transistor 21. The drain of the transistor 19 is connected to the drain of the transistor 22 and the gate of the transistor 23 and the gate of the transistor 19 is connected to ground Vss.
The transistor 20 has its source connected to the power supply potential Vcc and its gate connected to the word line WL. The source and drain of the transistor 21 are connected, respectively, to the power supply Vcc and word line WL. Further, the source of the transistor 22 is connected to the output terminal of the Vbb generator 16 and the gate of the transistor 22 is connected to the word line WL. The source of the transistor 23 is connected to the output terminal of the Vbb generator 16 and the drain of the transistor 23 is connected to the word line WL.
In the WL boostless type DRAM as shown in FIGS. 2 and 3, the transfer gate T is driven, at an address selected time, by the power supply Vcc not boosted. And at the address not-selected time the word line WL is biased to the negative potential Vbb by the word line driver circuit 13.
That is, the word line driver circuit 13 and DRAM peripheral circuit 14 are supplied with the same power supply potential Vcc. As shown in FIG. 3, when the word line WL is selected, if the transistor 21 is turned ON, the word line WL is brought up to the power supply potential Vcc. Unless the word line WL is boosted in this way, the write margin of "1" data becomes insufficient and, in the WL boostless type DRAM, the threshold voltage of the transfer gate T is set somewhat to a lower level.
If the threshold voltage of the transfer gate T is set somewhat to a lower level, more leak current flows, at the not-select time of the word line WL, from the capacitor C through the transfer gate T into the bit line BL. This causes the degeneration of the cell's pause characteristic (charge retaining characteristic).
At the not-select time, the word line WL is brought down to a lower negative potential Vbb (for example, -1 V) than the supply potential Vss. By doing so, the leak current of the transfer gate T can be reduced.
At the not-select time of the word line, however, a larger amount of discharge current flows from the word line WL into the Vbb generator 16. The Vbb generator 16, generating the potential Vbb, is required to be of a greater current supply capability type so as to drive a larger amount of discharge current. It is, therefore, unavoidable that the Vbb generator 16 be made a wider chip area. The Vbb generator 16 of such a wider chip area involves an increase in chip size, increase in dissipation power at a standby time and increase in manufacturing cost.
Such a conventional semiconductor memory device being such that the logic circuit and DRAM are integrated on one chip, if the gate oxide film of the transfer gate is so thickened as to secure the reliability of the DRAM section, then the gate oxide film of the transistor of the logic circuit section becomes also thickened because it is formed in the same process as the gate oxide film of the transfer gate T of the DRAM. In this case, the current drive capability of the transistor of the logic circuit section is lowered and an operation speed is more slowed down than when a logic LSI of the same generation is formed in its manufacturing process.
If any DRAM of such a type as not to boost the word line is adopted so as to solve the problem above, it is necessary to provide a Vbb generator of high current drive capability having a wider chip area. As a result, it involves an increase in the chip size, increase in dissipation power at a standby time and rise in manufacturing cost.